Thermal burn-in of semiconductor devices is a common industry practice to validate and assure the long term reliability of a component.
The process is split into two principal types:
a) 100% component burn-in
- Typically integrated as part of a production-level screening process to remove early fatigue failures.
b) Sample component burn-in
- Typically integrated as part of a component reliability or validation process flow.
Life Test Burn-In Chamber
Specification limits are established for each device based on the component datasheet and/or end application criteria to carefully “weed” out early life failures but not overstress the main batch.
These combinatorial factors are:
Bias condition – Static or Dynamic
Junction temperature – The product of both ambient and self-heating factors
Time – Relative to the application profile, normal usage or intended life expectancy.
For example a typical benchmark flow for a simple rectifier diode would static bias, 125 degrees C junction temperature for 168 hours.
Static bias applies only voltage and direct current as a broad means of applying general stress to the device and is generally suitable for simpler devices with a more uniform self-heating profile.
A more complex flow might include dynamic burn-in, which biases and switches inputs to simulate real-life worse case operation where higher complexity devices which may generate heat in a non-uniform manner or where behaviour must closely replicate field conditions.
We can perform burn-in following the below standards:
- MIL-STD-883 Method 1015 – ICs
- MIL-STD-750 Methods 1038, 1039, 1040, 1042 – Diodes and Transistors
- Mil-STD-202- Method 108
Typically used on a batch or new product qualification basis and depending on the specification or standard my be called Steady-State Life testing or High-Temperature Operating Life (HTOL) testing.
The purpose of this test is to evaluate the reliability of a device under high-temperature operation and over an extended time duration. The method and process used is similar to a 100% burn-in procedure where sample devices are exposed to a high-temperature level for a specific time and at a specific operating electrical bias. However the exposure time is always longer than the burn-in used for 100% screening. The sample size needs to be large enough and the life test specified such that results are not skewed by early life failures and instead are focusing on identification of any possible long term wear-out failure.
Failure mechanisms accelerated by SSL/HTOL include electromigration, hot carrier effects, charge effects, mobile ionic contamination and time-dependent dielectric breakdown
We can perform sample life based burn-in following the below standards:
- MIL-STD-883 Method 1005
- MIL-STD-883 Method 1015
- MIL-STD-883 Method 1016
- JEDEC JESD22-A108
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We offer a comprehensive selection of mechanical tests, from ball shear, die shear, wire bond pull to SEM inspection.
Semiconductor testing to Mil-PRF-38534 Class H & Class K.